The present disclosure relates generally to the field of switching power supplies, and more particularly to techniques for improved sensing of current flowing through the switching power supplies.
Switching power supplies such as a direct current-to-direct current (DC-DC) converter, switching regulator, and the like, have been used to provide direct current (DC) power to electrical/electronic devices such as integrated circuits (ICs), digital signal processors, radio frequency (RF) circuit devices such as cellular telephones, entertainment devices, portable computers, and the like, due to their improved power conversion efficiency compared to non-switching regulators. Switching DC-DC converters regulate an average DC output voltage by selectively storing energy in an energy storing element such as an inductor during a charge cycle, e.g., during an on time of a switching element. The energy stored in the inductor is selectively transferred to charge an output capacitor in discrete packets during a discharge cycle, e.g., during an off time of the switching element. Thus, the charge and discharge cycles are controlled by the switching element such as a field effect transistor (FET) by adjusting the on time and off time of a current flowing through the inductor.
Depending on the application, the switching regulators may be typically configured to operate in various well-known modes of control, including a voltage mode, a current mode, and a hysteric (or bang-bang) mode. In the current mode of control, a feedback control loop in a switching regulator is configured to measure a current flowing through the inductor and this current, upon being converted to a voltage, is used as feedback to control the output voltage. A well-known phenomenon associated with current mode switching regulators is a presence of an initial transient spike in the current when the power FET is turned on. The initial transient spike, which is generally caused by presence of parasitic capacitances and diode reverse recovery, may contribute to a loss of voltage regulation. A current blanking circuit having a particular time delay is often deployed to blank out the initial transient spike.
FIG. 1A illustrates a block diagram of a traditional current blanking circuit 100, according to prior art. In the depicted embodiment, the traditional current blanking circuit 100 includes a power FET 110 coupled in parallel with a sense FET 120. A drain of the power FET 110 is coupled to a drain of the sense FET 120 both being coupled to a switching input node 130, the gates of the power FET 110 and the sense FET 120 are coupled to one another, and a source of the power FET 110 is coupled to a ground reference 150. The operation of the power FET 110 and the sense FET 120 is controlled by a voltage signal that is provided by a gate driver 112 to the respective gates. A voltage level at the switching input node 130 switches between an on state and an off state, thereby enabling storing or discharging of energy in an energy storage element (not shown). A sense resistor 140 is coupled in series between a source of the sense FET 120 and the ground reference 150. When both the power FET 110 and the sense FET 120 are turned on, current flows through the parallel paths, the current being divided in proportion to the impedance of each path. A current 172 flowing through the power FET 110 is typically much greater than a current 174 flowing through the sense FET 120, e.g., by a factor of tens of thousands. An amplifier 160 converts the current sensed by the sense FET 120 into a voltage Vlfb_sen 162.
FIG. 1B illustrates transient waveforms associated with the traditional current blanking circuit 100 described with reference to FIG. 1A, according to prior art. Referring to FIGS. 1A and 1B, at time t0 180 when the power FET 110 is turned on, there is a leading edge spike 170 and 171 respectively on the transient waveforms of the current 172 flowing through the power FET 110 and the current 174 flowing through the sense FET 120. The leading edge spike 170 and 171 are caused by the presence of parasitic capacitances and by the reverse recovery phenomenon associated with the FET switches. The presence of the leading edge spike 170 and 171 causes an output of the amplifier 160 to take a large amount of time (e.g., from t1 181 to t2 182) to settle down and generate a voltage equivalent value that is indicative of the current flowing through the power FET 110.
The traditional current blanking circuit 100 includes a delay unit 180 and an output blanking switch 183 in a feedforward path to reduce the impact of the leading edge spike 170. The delay unit 180 and the output blanking switch 183 are operable to blank out or zero out the output Vlfb_sen 162 of the amplifier 160 for a predetermined time (referred to as the current blanking time). Voltage at Vlfb_sen 162 is shown without blanking and with blanking between t1 181 and t2 182. The effects of the leading edge spike 170 on the amplifier 160 are blanked by controlling a voltage at the gate of the output blanking switch 183 during the current blanking time period. It is desirable that the current blanking time period is sufficient to cover delay associated with the gate driver 112 and the settling down time of the amplifier 160 under various process and temperature conditions. The delay unit 180 may be implemented as an analog circuit or a digital circuit.
Maintaining a particular duty cycle or a desired minimum duty cycle to provide the lowest programmable output voltage with the traditional current blanking circuit 100 with the delay unit 180 and an output blanking switch 180 may be difficult for all process and temperature corners. For example, a digital circuit implementation of the delay unit 180 often provides a predetermined, fixed delay time, and an analog circuit implementation using resistor and capacitor elements is inherently subject to parametric variations due to process and temperature conditions, which affect the delay time. In addition, implementation of the traditional current blanking circuit 100 is not area efficient since the delay unit 180 and the output blanking switch 180 utilize greater silicon area compared to another traditional circuit without the current blanking feature. Furthermore, as described earlier, the settling time of the amplifier 160, caused due to the initial current spike in the sense current, may vary with different process and temperature conditions.